library ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay is port (
clk     : in std_ulogic;
delay_in   : in std_ulogic_vector(7 downto 0);
delay_out  : out std_ulogic_vector(7 downto 0)
		     );
end entity ;
architecture rtl of delay is
       signal temp,temp1,temp2,temp3,temp4,temp5,temp6,temp7,temp8,temp10,temp9 : std_ulogic_vector(7 downto 0);	
begin 
  --1
	process(clk)
	begin 
		if clk'event and clk = '1' then 
			temp <= delay_in;
		end if;
	end process;
--2
	process(clk)
	begin 
		if clk'event and clk = '1' then 
			temp1 <= temp ;
		end if ;
	end process ;
	--3
	process(clk)
	begin 
		if clk'event and clk = '1' then 
			temp2 <= temp1;
		end if;
	end process;
	--4
	process(clk)
	begin 
		if clk'event and clk = '1' then 
			temp3 <= temp2;
		end if;
	end process;
	--5
	process(clk)
	begin 
		if clk'event and clk = '1' then 
			temp4 <= temp3;
		end if;
	end process;
	--6
	process(clk)
	begin 
		if clk'event and clk = '1' then 
			temp5 <= temp4;
		end if;
	end process;
	process(clk)
	begin 
		if clk'event and clk = '1' then 
			temp6 <= temp5;
		end if;
	end process;
	--7
	process(clk)
	begin 
		if clk'event and clk = '1' then 
			temp7 <= temp6;
		end if;
	end process;
	--8
	process(clk)
	begin 
		if clk'event and clk = '1' then 
			temp8 <= temp7;
		end if;
	end process;
	--9
	process(clk)
	begin 
		if clk'event and clk = '1' then 
			temp9 <= temp8;
		end if;
	end process;
	--10
	process(clk)
	begin 
		if clk'event and clk = '1' then 
			temp10 <= temp9;
		end if;
	end process;
	--11
	process(clk)
	begin 
		if clk'event and clk = '1' then 
			delay_out <= temp9;
		end if;
	end process;
end rtl;


